Display device having more reliable image display

ABSTRACT

A display device array substrate includes first and second light blocking regions, a first insulation layer disposed on the first light blocking region, a second insulation layer disposed on the second light blocking region, a light blocking member including a first part disposed on the first light blocking region and the first insulation layer, a second part disposed on the second light blocking region and the second insulation layer, and a third part disposed on a boundary between the first and second light blocking regions. A minimum height from an upper surface of the first insulation substrate to an upper surface of the third part is lower than a minimum height from the upper surface of the first insulation substrate to an upper surface of the first part and a minimum height from the upper surface of the first insulation substrate to an upper surface of the second part.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No.10-2015-0111045 filed on Aug. 6, 2015 in the Korean IntellectualProperty Office, the disclosure of which is incorporated herein byreference in its entirety.

BACKGROUND

1. Technical Field

Embodiments of the present inventive concept relate generally to flatpanel displays. More specifically, embodiments of the present inventiveconcept relate to a flat panel display device having more reliable imagedisplay.

2. Description of the Related Art

A liquid crystal display device is one of the currently most widely usedflat panel display devices, and may include two substrates facing eachother with a liquid crystal layer interposed between the two substrates.Since the thickness of the liquid crystal layer may affect transmittanceof light which passes through the liquid crystal layer, a spacer membermay be interposed between the two substrates so as to maintain a uniformgap between the two substrates.

When a force from an external source is applied to the liquid crystaldisplay device, the spacer member may be deformed to cause a change inthe gap between the two substrates, which in turn may lead to a changein the light transmittance of the liquid crystal layer.

SUMMARY

Aspects of the present inventive concept provide a display device withimproved reliability.

However, embodiments of the present inventive concept are not restrictedto those set forth herein. Other embodiments of the present inventiveconcept which are not mentioned herein will become more apparent to aperson skilled in the art to which the present inventive conceptpertains by referencing the detailed description of the presentinventive concept given below.

According to an aspect of the present inventive concept, there isprovided a display device. The display device includes: an arraysubstrate; a counterpart substrate facing the array substrate; and aliquid crystal layer interposed between the array substrate and thecounterpart substrate. The array substrate includes: a first insulationsubstrate including a first pixel region having a first light blockingregion, and a second pixel region disposed adjacent to the first pixelregion in a first direction and having a second light blocking region; afirst insulation layer disposed on the first light blocking region ofthe first insulation substrate; a second insulation layer disposed onthe second light blocking region of the first insulation substrate; alight blocking member including a first part disposed on the first lightblocking region of the first insulation substrate and on the firstinsulation layer, a second part disposed on the second light blockingregion of the first insulation substrate and on the second insulationlayer, and a third part disposed on a boundary between the first lightblocking region of the first insulation substrate and the second lightblocking region of the first insulation substrate, the third part beingconnected to the first part and the second part; and a spacer memberdisposed on the light blocking member and contacting the counterpartsubstrate. A minimum height from an upper surface of the firstinsulation substrate to an upper surface of the third part is lower thana minimum height from the upper surface of the first insulationsubstrate to an upper surface of the first part and lower than a minimumheight from the upper surface of the first insulation substrate to anupper surface of the second part.

According to another aspect of the present inventive concept, there isprovided a display device. The display device includes: an arraysubstrate; a counterpart substrate facing the array substrate; and aliquid crystal layer interposed between the array substrate and thecounterpart substrate. The array substrate includes a first insulationsubstrate having a first pixel region having a first light blockingregion, and a second pixel region disposed adjacent to the first pixelregion in a first direction and having a second light blocking region;the counterpart substrate includes: a second insulation substrate; alight blocking member disposed on the second insulation substrate facingthe array substrate and overlapping the first light blocking region andthe second light blocking region; and a spacer member which is disposedon the light blocking member and which contacts the array substrate. Thelight blocking member includes a first part, a second part differentfrom the first part, and a third part different from the first part andthe second part. A minimum height from one surface of the secondinsulation substrate to an upper surface of the third part is lower thana minimum height from the one surface of the second insulation substrateto an upper surface of the first part and lower than a minimum heightfrom the one surface of the second insulation substrate to an uppersurface of the second part.

Specific features of the embodiments are included in the detaileddescription and drawings.

The embodiments of the present inventive concept may at least provideeffects described as follows.

That is, a display device with improved reliability may be provided.

However, effects of the present inventive concept are not restricted tothe exemplary embodiments set forth herein and more diverse effects areincluded in this description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating an equivalent circuit of onepixel of a display device according to an embodiment of the presentinventive concept;

FIG. 2 is a schematic plan view of an array substrate included in thedisplay device according to an embodiment of the present inventiveconcept, and more specifically, a plan view schematically illustrating astructure of one pixel;

FIG. 3 is a schematic cross sectional view of the display deviceaccording to an embodiment of the present inventive concept, taken alongline L3-L3′ of FIG. 2;

FIG. 4 is a schematic cross sectional view of the display deviceaccording to an embodiment of the present inventive concept, taken alongline L4-L4′ of FIG. 2;

FIG. 5 is a plan view schematically illustrating three pixels of thedisplay device according to an exemplary embodiment of the presentinventive concept;

FIG. 6 is a plan view schematically illustrating an exemplaryarrangement of insulation layers, a light blocking member, data linesand shield electrodes in the display device shown in FIG. 5;

FIG. 7 is a schematic cross sectional view taken along line M1-M1′ ofFIG. 5 and FIG. 6;

FIG. 8 is an enlarged perspective view illustrating a part of the lightblocking member shown in FIG. 7;

FIG. 9 is a schematic cross sectional view taken along line M2-M2′ ofFIG. 5 and FIG. 6;

FIG. 10 is a plan view of a modified embodiment of the display deviceshown in FIG. 5, schematically illustrating another exemplaryarrangement of insulation layers, a light blocking member, data linesand shield electrodes in the display device;

FIG. 11 is a schematic cross sectional view taken along line M1-M1′ ofFIG. 5 and FIG. 10;

FIG. 12 is a schematic cross sectional view taken along line M2-M2′ ofFIG. 5 and FIG. 10;

FIG. 13 is a schematic cross sectional view of the display deviceaccording to another embodiment of the present inventive concept, takenalong line L3-L3′ of FIG. 2;

FIG. 14 is a schematic cross sectional view of the display deviceaccording to another embodiment of the present inventive concept, takenalong line L4-L4′ of FIG. 2;

FIG. 15 is a plan view schematically illustrating an exemplaryarrangement of insulation layers, a light blocking member, data linesand shield electrodes in the display device according to anotherembodiment of the present inventive concept;

FIG. 16 is a schematic cross sectional view taken along line M1-M1′ ofFIG. 5 and FIG. 15;

FIG. 17 is an enlarged perspective view illustrating a part of the lightblocking member shown in FIG. 16;

FIG. 18 is a schematic cross sectional view taken along line M2-M2′ ofFIG. 5 and FIG. 16;

FIG. 19 is a plan view of a modified embodiment of the display deviceshown in FIG. 15, schematically illustrating another exemplaryarrangement of insulation layers, a light blocking member, data linesand shield electrodes in the display device;

FIG. 20 is a schematic cross sectional view taken along line M1-M1′ ofFIG. 5 and FIG. 19; and

FIG. 21 is a schematic cross sectional view taken along line M2-M2′ ofFIG. 5 and FIG. 19.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Features of the inventive concept and methods of accomplishing the samemay be understood more readily by reference to the following detaileddescription of embodiments and the accompanying drawings. The inventiveconcept may, however, be embodied in many different forms and should notbe construed as being limited to the embodiments set forth herein.Rather, these embodiments are provided so that this disclosure will bethorough and complete and will fully convey the concept of the inventiveconcept to those skilled in the art, and the inventive concept will onlybe defined by the appended claims. Like reference numerals refer to likeelements throughout the specification.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the inventiveconcept. As used herein, the singular forms “a”, “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof.

It will be understood that when an element or layer is referred to asbeing “on”, “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on”, “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, components, regions, layersand/or sections, these elements, components, regions, layers and/orsections should not be limited by these terms. These terms are only usedto distinguish one element, component, region, layer or section fromanother region, layer or section. Thus, a first element, component,region, layer or section discussed below could be termed a secondelement, component, region, layer or section without departing from theteachings of the inventive concept.

Spatially relative terms, such as “beneath”, “below”, “lower”, “above”,“upper”, and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which the present application belongs.It will be further understood that terms, such as those defined incommonly used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of the relevant artand this specification and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

The various Figures are not necessarily to scale. All numerical valuesare approximate, and may vary. All examples of specific materials andcompositions are to be taken as nonlimiting and exemplary only. Othersuitable materials and compositions may be used instead.

Embodiments set forth herein are described in the specification anddepicted in the drawing in terms of an exemplary vertical alignment modeor patterned vertical alignment mode display device, but the presentdisclosure is not limited thereto. The present inventive concept may beapplied to various display devices such as an in-plane switching (IPS)mode display device, a plane-line switching (PLS) mode display device, afringe-field switching (FFS) mode display device, a twisted nematic (TN)mode display device and an electrically-controlled birefringence (ECB)mode display device.

Furthermore, embodiments set forth herein are described in thespecification and depicted in the drawings in terms of a display devicehaving a top common electrode configuration, but the present disclosureis not limited thereto. The present inventive concept may, for example,be applied to a display device having a bottom common electrodeconfiguration.

Embodiments of the present inventive concept will hereinafter beexplained with reference to the drawings.

FIG. 1 is a circuit diagram illustrating an equivalent circuit of onepixel of a display device according to an embodiment of the presentinventive concept.

Referring to FIG. 1, one pixel of the display device according to anembodiment of the present inventive concept may include two subpixels P1and P2. Furthermore, one pixel of the display device according to anembodiment of the present inventive concept may include a gate line GLnfor transmitting a gate signal, a data line DLm for transmitting a datavoltage, a sustain electrode line SLn for applying a constant sustainvoltage Vc, and a first thin film transistor Tr1, a second thin filmtransistor Tr2 and a third thin film transistor Tr3.

The first thin film transistor Tr1 and the second thin film transistorTr2 may be connected to the same gate line GLn and same data line DLm.Furthermore, the third thin film transistor Tr3 may be connected to thegate line GLn like the first thin film transistor Tr1 and the secondthin film transistor Tr2, and to the second thin film transistor Tr2 andthe sustain electrode line SLn.

One pixel may include two subpixels P1 and P2, and the first subpixel P1may include a first liquid crystal capacitor Clc1 connected to the firstthin film transistor Tr1 and the second subpixel P2 may include a secondliquid crystal capacitor Clc2 connected to the second thin filmtransistor Tr2.

The first thin film transistor Tr1 may be included in the first subpixelP1, and the second and third thin film transistors Tr2 and Tr3 may beincluded in the second subpixel P2.

The first thin film transistor Tr1 may have a first terminal connectedto the gate line GLn, a second terminal connected to the first data lineDLm, and a third terminal connected to the first liquid crystalcapacitor Clc1.

Specifically, the third terminal of the first thin film transistor Tr1may be connected to a first subpixel electrode (not shown in thedrawing) of the first liquid crystal capacitor Clc1.

The second thin film transistor Tr2 may have a first terminal connectedto the gate line GLn, a second terminal connected to the first data lineDLm, and a third terminal connected to the second liquid crystalcapacitor Clc2.

Specifically, the third terminal of the second thin film transistor Tr2may be connected to a second subpixel electrode (not shown in thedrawing) of the second liquid crystal capacitor Clc2.

The third thin film transistor Tr3 may have a first terminal connectedto the gate line GLn, a second terminal connected to the sustainelectrode line SLn, and a third terminal connected to the third terminalof the second thin film transistor Tr2.

The display device according to an exemplary embodiment of the presentinventive concept may operate as follows. When a gate on voltage isapplied to the gate line GLm, each of the first, the second and thethird thin film transistors Tr1, Tr2 and Tr3 are turned on, and thefirst liquid crystal capacitor Clc1 and the second liquid crystalcapacitor Clc2 may be charged with the data voltage transmitted throughthe first data line DLm. In this case, the data voltage applied to thefirst subpixel electrode and the second subpixel electrode are identicalwith each other, and the first liquid crystal capacitor Clc1 and thesecond liquid crystal capacitor Clc2 may be charged by the same voltagevalue, which is a difference between a common voltage Vcom and the datavoltage.

When the third thin film transistor Tr3 is turned on, the data voltagetransmitted to the second subpixel P2 through the first data line DLmmay be divided through the third thin film transistor Tr3 connected inseries with the second thin film transistor Tr2. In this case, thevoltage may be distributed based on the size of channels of the secondthin film transistor Tr2 and the third thin film transistor Tr3. Thus,even when the data voltages transmitted to the first subpixel P1 and thesecond subpixel P2 through the first data line DLm are the same, thevoltages charged in the first liquid crystal capacitor Clc1 and thesecond liquid crystal capacitor Clc2 may be different from each other.That is, the voltage charged in the second liquid crystal capacitor Clc2may be lower than the voltage charged in the first liquid crystalcapacitor Clc1.

Consequently, the voltages charged in the first subpixel P1 and thesecond subpixel P2 of one pixel may be different from each other,thereby improving side visibility. The sustain voltage Vc may have alevel higher than the level of the common voltage Vcom. For example,when the common voltage Vcom is approximately 7V, the sustain voltage Vcmay be approximately 8V to 11V, but the present disclosure is notlimited thereto.

FIG. 2 is a schematic plan view of an array substrate included in thedisplay device according to an embodiment of the present inventiveconcept, and more specifically, a plan view schematically illustrating astructure of one pixel represented in FIG. 1. FIG. 3 is a schematiccross sectional view of the display device including the array substrateof FIG. 2, taken along line L3-L3′ of FIG. 2. FIG. 4 is a schematiccross sectional view of the display device including the array substrateof FIG. 2, taken along line L4-L4′ of FIG. 2.

Referring to FIG. 2 to FIG. 4, a display device 1 may include an arraysubstrate 100, a counterpart substrate 200 facing the array substrate100, and a liquid crystal layer 300 interposed between the arraysubstrate 100 and the counterpart substrate 200, and may further includea pair of polarizers (not shown) attached to outer surfaces of the arraysubstrate 100 and the counterpart substrate 200.

First, the array substrate 100 will be described.

A first insulation substrate SUB1 may be a transparent insulationsubstrate. For example, the first insulation substrate SUB1 may beformed of a glass substrate, a quartz substrate, a transparent resinsubstrate and the like. Furthermore, the first insulation substrate SUB1may include polymers or plastics with high heat resistance. In someembodiments, the first insulation substrate SUB1 may have flexibility.That is, the first insulation substrate SUB1 may be a transformable orflexible substrate which can be rolled, folded or bent.

The first insulation substrate SUB1 may include a pixel region in whichone pixel is disposed, and the pixel region may be defined as a regionin which a pixel electrode is provided. For example, as shown in FIG. 2,the first insulation substrate SUB1 may include a first pixel regionPA1. The first pixel region PA1 may include a first light blockingregion BA1.

The gate line GLn may be disposed on the first insulation substrateSUB1. The gate line GLn may mainly extend in a first direction (forexample, an X direction) and transmit a gate signal.

A first gate electrode GE1 and a second gate electrode GE2, which extendfrom the gate line GLn and are connected to each other, may be disposedon the first insulation substrate SUB1. Furthermore, a third gateelectrode GE3, which extends from the gate line GLn and is spaced apartfrom the first gate electrode GE1 and the second gate electrode GE2, mayalso be disposed on the first insulation substrate SUB1. The first, thesecond and the third gate electrodes GE1, GE2 and GE3 may be connectedto the same gate line GLn, and thus the same gate signal may be appliedto the first, the second and the third gate electrodes GE1, GE2 and GE3.

The gate line GLn, the first gate electrode GE1, the second gateelectrode GE2 and the third gate electrode GE3 may includealuminum-based metal such as aluminum (Al) or aluminum alloy,silver-based metal such as silver (Ag) or silver alloy, copper-basedmetal such as copper (Cu) or copper alloy, molybdenum-based metal suchas molybdenum (Mo) or molybdenum alloy, chrome (Cr), tantalum (Ta),titanium (Ti) and the like. The gate line GLn, the first gate electrodeGE1, the second gate electrode GE2 and the third gate electrode GE3 mayhave a single layer structure, or a multi-layer structure including atleast two conductive layers having different physical properties. Oneamong these multiple conductive layers may be made of low-resistancemetal, for example, aluminum-based metal, silver-based metal,copper-based metal and the like, so as to reduce a signal delay orvoltage drop. The other conductive layers may be made of differentmaterials, specifically materials having superior contactcharacteristics with indium tin oxide (ITO) and indium zinc oxide (IZO),for example, molybdenum-based metal, chrome (Cr), titanium (Ti),tantalum (Ta) and the like. An example of such combination may include alower chrome layer and an upper aluminum layer, or a lower aluminumlayer and an upper molybdenum layer. However, the present disclosure isnot limited thereto, and the gate line GLn, the first gate electrodeGE1, the second gate electrode GE2 and the third gate electrode GE3 maybe made of various metals and other conductors.

A gate insulation layer GI may be provided on the gate line GLn and thefirst, the second and the third gate electrodes GE1, GE2 and GE3. Thegate insulation layer GI may be made of an inorganic insulationmaterial, for example, silicon oxide, silicon nitride, siliconoxynitride and the like. The gate insulation layer GI may be formed as asingle layer structure, or a multi-layer structure including at leasttwo insulation layers having different physical properties.

A first semiconductor layer SM1, a second semiconductor layer SM2 and athird semiconductor layer SM3 may be formed on the gate insulation layerGI. The first semiconductor layer SM1 may be provided on the first gateelectrode GE1, the second semiconductor layer SM2 may be provided on thesecond gate electrode GE2, and the third semiconductor layer SM3 may beprovided on the third gate electrode GE3. In some embodiments, asemiconductor pattern SMd may further be provided beneath data lines DLmand DLm+1. Each of the first second semiconductor layer SM1, the secondsemiconductor layer SM2, the third semiconductor layer SM3 and thesemiconductor pattern SMd may include amorphous silicon, polycrystallinesilicon or an oxide semiconductor.

A plurality of ohmic contact members Oha1, Ohb2, Ohb3, Ohb1, Ohb2, Ohb3and Ohd may be provided on the first semiconductor layer SM1, the secondsemiconductor layer SM2 and the third semiconductor layer SM3. Theplurality of ohmic contact members Oha1, Ohb2, Ohb3, Ohb1, Ohb2, Ohb3and Ohd may include source ohmic contact members Oha1, Ohb2 and Ohb3provided beneath the first, the second and the third source electrodesSE1, SE2 and SE3, and drain ohmic contact members Ohb1, Ohb2 and Ohb3provided beneath the first, the second and the third drain electrodesDE1, DE2 and DE3 to be described later. The data ohmic contact memberOhd may optionally be provided beneath the data lines DLm and DLm+1, andthe data ohmic contact member Ohd may be interposed between the datalines DLm and DLm+1 and the semiconductor pattern SMd. In someembodiments, the plurality of ohmic contact members Oha1, Ohb2, Ohb3,Ohb1, Ohb2, Ohb3 and Ohd may be made of n+ hydrated amorphous silicon orthe like, which is highly doped with n-type impurities, or silicide. Insome embodiments, when the first semiconductor layer SM1, the secondsemiconductor layer SM2, the third semiconductor layer SM3 and thesemiconductor pattern SMd are oxide semiconductors, the ohmic contactmembers Oha1, Ohb2, Ohb3, Ohb1, Ohb2, Ohb3 and Ohd may be omitted.

The data lines DLm and DLm+1, the first source electrode SE1, the firstdrain electrode DE1, the second source electrode SE2, the second drainelectrode DE2, the third source electrode SE3 and the third drainelectrode DE3 may be formed on the ohmic contact members Oha1, Ohb2,Ohb3, Ohb1, Ohb2, Ohb3 and Ohd and the gate insulation layer GI.

The data lines DLm and DLm+1 may transmit data voltages, and mainlyextend in a second direction (for example, Y direction) so as tointersect the gate line GLn.

The first source electrode SE1 may be positioned above the first gateelectrode GE1 from the first data line DLm. In some embodiments, thefirst source electrode SE1 may have a C shape above the first gateelectrode GE1, but the present disclosure is not limited thereto and anyshape is contemplated.

The first drain electrode DE1 may be spaced apart from the first sourceelectrode SE1 above the first gate electrode GE1. A channel may thus beformed in a part of the first semiconductor layer SM1 exposed throughthe gap between the first source electrode SE1 and the first drainelectrode DE1.

The second source electrode SE2 may be positioned above the second gateelectrode GE2 from the data line DLm. The second source electrode SE2may have a C shape above the second gate electrode GE2, but the presentdisclosure is not limited thereto and any shape is contemplated.

The second drain electrode DE2 may be spaced apart from the secondsource electrode SE2 above the second gate electrode GE2. A channel maytherefore be formed in a part of the second semiconductor layer SM2exposed through the gap between the second source electrode SE2 and thesecond drain electrode DE2. The second drain electrode DE2 may have awide extended part DE2 a.

The third source electrode SE3 may be connected to the second drainelectrode DE2, and spaced apart from the third drain electrode DE3 abovethe third gate electrode GE3. A channel may be formed in a part of thethird semiconductor layer SM3 exposed through the gap between the thirdsource electrode SE3 and the third drain electrode DE3.

The drain electrode DE3 may be positioned above the third gate electrodeGE3. The third drain electrode DE3 may be connected to the sustainelectrode line SLn, which will be described later, so as to receive aconstant voltage, for example, the sustain voltage Vc.

The data lines DLm and DLm+1, the first source electrode SE1, the firstdrain electrode DE1, the second source electrode SE2, the second drainelectrode DE2, the third source electrode SE3 and the third drainelectrode DE3 may be made of one or more conductive materials such asaluminum, copper, silver, molybdenum, chrome, titanium, tantalum or analloy thereof. Each of these elements may have a multi-layer structureformed of a lower layer (not shown) made of refractory metal and thelike and a low-resistance upper layer (not shown) formed on the lowerlayer, but the present disclosure is not limited thereto.

The first gate electrode GE1, the first semiconductor layer SM1, thefirst source electrode SE1 and the first drain electrode DE1 describedabove may together form the first thin film transistor Tr1. Furthermore,the second gate electrode GE2, the second semiconductor layer SM2, thesecond source electrode SE2 and the second drain electrode DE2 maycollectively form the second thin film transistor Tr2, while the thirdgate electrode GE3, the third semiconductor layer SM3, the third sourceelectrode SE3 and the third drain electrode DE3 may collectively formthe third thin film transistor Tr3.

A first passivation layer PA1 may be provided on the data lines DLm andDLm+1, the first, the second and the third source electrodes SE1, SE2and SE3 and the first, the second and the third drain electrodes DE1,DE2 and DE3. The first passivation layer PA1 may include an organicinsulation material or an inorganic insulation material such as siliconoxide, silicon nitride, silicon oxynitride and the like. The firstpassivation layer PA1 may protect the first, the second and the thirdthin film transistors Tr1, Tr2 and Tr3, and prevent material of aninsulation layer ILA, which will be described later, from beingintroduced into the first, the second and the third semiconductor layersSM1, SM2 and SM3.

A first insulation layer ILA1 may be provided on the first passivationlayer PA1. In some embodiments, the first insulation layer ILA1 may havea function of flattening an upper portion of the first passivation layerPA1. The first insulation layer ILA1 may include a photosensitivematerial. The photosensitive material may be a photosensitive organicmaterial, for example, a photoresist. In some embodiments, insulationlayer ILA1 may include a negative type photoresist in which a partexposed to light is hardened, or a positive type photoresist in which apart not exposed to light is hardened.

The first insulation layer ILA1 may further include a color pigment. Forexample, the first insulation layer ILA1 may include a color pigmentwhich passes light in a wavelength range corresponding to a specificcolor. That is, the first insulation layer ILA1 may be a color filter.In an exemplary embodiment, the color filter may present or pass aprimary color such as a red color, a green color or a blue color.However, the colors need not be limited to these particular primarycolors, and the color filter may instead present any one of cyan,magenta, yellow and white-based colors, or any other color, primary orotherwise, as desired. When the first insulation layer ILA1 includes acolor pigment, the first insulation layer ILA1 may at least partiallyoverlap the insulation layer of a neighboring pixel above the data linesDLm and DLm+1. For example, the first insulation layer ILA1 may at leastpartially overlap a second insulation layer ILA2 in a neighboring pixelregion (or a second pixel region PA2) above the second data line DLm+1.However, the present disclosure is not limited thereto, and the firstinsulation layer ILA1 need not necessarily include a color pigment. Inanother embodiment, a separate color filter may be provided on the arraysubstrate 100, or a color filter may be provided on the counterpartsubstrate 200.

The second passivation layer PA2 may be provided on the first insulationlayer ILA1. The second passivation layer PA2 may include an inorganicinsulation material such as silicon oxide, silicon nitride, siliconoxynitride and the like. The second passivation layer PA2 may preventthe first insulation layer ILA1 from separating, and inhibit the liquidcrystal layer 300 from being contaminated by an organic material such asa solvent introduced from the first insulation layer ILA1. Thus,afterimage defects which may occur during driving of the display device1 can be further prevented.

A first contact hole CT1 for exposing a part of the first drainelectrode DE1 and a second contact hole CT2 for exposing a part of thesecond drain electrode DE2 may be formed in the first passivation layerPA1, the first insulation layer ILA1 and the second passivation layerPA2.

The pixel electrode PE may be provided on the second passivation layerPA2, and the pixel electrode PE may be provided in the first pixelregion PA1 of the first insulation substrate SUB1. That is, the firstpixel region PA1 may be defined as a part of the first insulationsubstrate SUB1 corresponding to the pixel electrode PE. The pixelelectrode PE may include a first subpixel electrode PE1 and a secondsubpixel electrode PE2. When viewed in plan view (i.e. the view of FIG.2), the first subpixel electrode PE1 and the second subpixel electrodePE2 may be arranged along the second direction (or the Y direction) withthe gate line GLn interposed therebetween. That is, in an exemplaryembodiment, the first subpixel electrode PE1 may be provided above thegate line GLn, and the second subpixel electrode PE2 may be providedunder the first subpixel electrode PE1 and below the gate line GLn. Thefirst light blocking region BA1, which will be described later, may bedefined as a region between the first subpixel electrode PE1 and thesecond subpixel electrode PE2.

The first subpixel electrode PE1 may be connected to the first drain DE1through the first contact hole CT1, and the second subpixel electrodePE2 may be connected to the second drain DE2 through the second contacthole CT2.

The first subpixel electrode PE1 and the second subpixel electrode PE2may receive a data voltage respectively from the first drain electrodeDE1 and the second drain electrode DE2. In this case, the data voltageapplied to the second drain electrode DE2 may be divided through thethird source electrode SE3, and the magnitude of the second subpixelvoltage applied to the second subpixel electrode PE2 may therefore besmaller than the magnitude of the first subpixel voltage applied to thefirst subpixel electrode PE1. More precisely, when the data voltagesapplied to the first subpixel electrode PE1 and the second subpixelelectrode PE2 are positive (+), the magnitude of the voltage applied tothe second subpixel electrode PE2 is smaller than the magnitude of thevoltage applied to the first subpixel electrode PE1. When, on thecontrary, the data voltages applied to the first subpixel electrode PE1and the second subpixel electrode PE2 are negative (−), the magnitude ofthe first subpixel voltage applied to the first subpixel electrode PE1may be smaller than the magnitude of the second subpixel voltage appliedto the second subpixel electrode PE2.

The first subpixel electrode PE1 may include a first stem PE1 a and aplurality of first branches PE1 b protruding and extending outward fromthe first stem PE1 a. The first stem PE1 a may be shaped in any manner.For example, as shown in FIG. 2, the first stem PE1 a may have a crossshape. In this case, the first subpixel may be divided into four domainsby the first stem PE1 a.

The first branches PE1 b may extend in different directions in eachdomain. The first branches PE1 b may extend in parallel with each otherin each domain, and may be spaced apart from each other. Adjacent firstbranches PE1 b may be spaced apart on a micrometer spacing basis so asto form a plurality of fine slits.

The subpixel electrode PE1 may be made of a transparent conductivematerial. For example, the subpixel electrode PE1 may be made of amaterial such as ITO, IZO, ITZO or AZO.

Liquid crystal molecules of the liquid crystal layer 300 over the firstsubpixel electrode PE1 may be pretilted in different directions in eachdomain by the plurality of fine slits. For example, the liquid crystalmolecules may be pretilted in four directions headed toward the firststem PE1 a. Thus, four domains in which liquid crystal molecules arealigned in different directions may be formed in the liquid crystallayer 300. As described above, varying the pretilt direction of theliquid crystal molecules may enable the display device 1 to have a widereference view angle.

The second subpixel electrode PE2 may include a second stem PE2 a and aplurality of second branches PE2 b protruding and extending away fromthe second stem PE2 a. That is, the second subpixel electrode PE2 mayhave a configuration substantially the same as that of the subpixelelectrode PE1. Therefore, detailed description of the configuration ofthe second subpixel electrode PE2 will be omitted.

The second subpixel electrode PE2 may have an area larger than the areaof the first subpixel electrode PE1 when viewed in plan view.

The sustain electrode line SLn may be further provided on the firstinsulation substrate SUB1. The sustain electrode line SLn may extend ina direction (for example, a horizontal direction) substantially the sameas that of the gate line GLn. The sustain electrode line SLn may beformed to enclose at least a part of the pixel electrode PE, which willbe described later. For example, the sustain electrode line SLn mayfurther include a first sustain electrode SLna, a second sustainelectrode SLnb and a third sustain electrode SLnc enclosing a part ofthe first subpixel electrode PE1. Furthermore, the sustain electrodeline SLn may further include a sustain electrode extension SLnpextending from the first sustain electrode SLna or the second sustainelectrode SLnb. A sustain electrode contact hole CT3, which is a thirdcontact hole for exposing a part of the sustain electrode extension SLnpand a part of the third drain electrode DE3, may be formed in the gateinsulation layer GI, the first passivation layer PA1, the insulationlayer ILA and the second passivation layer PA2, and the sustainelectrode contact hole CT3 may be covered by a connection member TE. Theconnection member TE may electrically interconnect the sustain electrodeextension SLnp and the third drain electrode DE3 which are exposedthrough the sustain electrode contact hole CT3. In some embodiments, theconnection member TE may be made of a material that is the same as thatof the pixel electrode PE, and the connection member TE and the pixelelectrode PE may be provided in the same layer.

The sustain electrode line SLn may further include a fourth sustainelectrode SLnd, a fifth sustain electrode SLne and a sixth sustainelectrode SLnf enclosing a part of the second subpixel electrode PE2. Insome embodiments, the sustain electrode extension SLnp may extend to thespace between the pixel electrode PE and the gate line GLn when viewedin plan view. Furthermore, in some embodiments, the first sustainelectrode SLna, the second sustain electrode SLnb, the fourth sustainelectrode SLnd and the fifth sustain electrode SLne may be interposedbetween the pixel electrode PE and the data lines DLm and DLm+1 whenviewed in plan view.

In an exemplary embodiment, the sustain electrode line SLn, the gateline GLn and the first, the second and third gate electrodes GE1, GE2and GE3 may be provided in the same layer and be made of the samematerial. That is, in the exemplary embodiment, the sustain electrodeline SLn may be interposed between the first insulation substrate SUB1and the gate insulation layer GI, and made of a material that is thesame as that of the gate line GLn.

A shield electrode SHE may be provided on the second passivation layerPA2. The shield electrode SHE may be physically spaced apart from thefirst subpixel electrode PE1 and the second subpixel electrode PE2, andthe shield electrode SHE, the first subpixel electrode PE1 and thesecond subpixel electrode PE2 may be provided in the same layer. Thatis, like the first subpixel electrode PE1 and the second subpixelelectrode PE2, the shield electrode SHE may be provided directly on thesecond passivation layer PA2 so as to directly contact the secondpassivation layer PA2. The shield electrode SHE may be made of atransparent conductive material, and may also be made of the samematerial as that of the pixel electrode PE. In some embodiments, theshield electrode SHE, the first subpixel electrode PE1 and the secondsubpixel electrode PE2 may be formed simultaneously through aphotolithography process using a single mask.

The shield electrode SHE may be provided on a part of an upper surfaceof the second passivation layer PA2 corresponding to the data lines DLmand DLm+1, and may overlap the data lines DLm and DLm+1. In an exemplaryembodiment, the shield electrode SHE may be arranged to correspond to aboundary between the pixel regions of the first insulation substrateSUB1. For example, the shield electrode SHE may be provided on aboundary region EA of the first insulation substrate SUB1, which is aboundary between the first pixel region PA1 and its neighboring secondpixel region PA2 in the first direction (or X direction). The shieldelectrode SHE may cover the first data line DLm when viewed in planview. In some embodiments, a voltage having a level or magnitude thesame as that of the common voltage applied to the common electrode CE,which will be described later, may be applied to the shield electrodeSHE.

There exists a possibility of misalignment of liquid crystal moleculesin a portion between the data lines DLm and DLm+1 and the pixelelectrode PE, since a relatively weak electric field may be generatedbetween the pixel electrode PE and the common electrode CE in thatportion, which will be described later.

In the display device 1 according to the present embodiment, a voltagehaving a level the same as that of the voltage applied to the commonelectrode CE, for example a common voltage, may be applied to the shieldelectrode SHE. Thus, no electric field may be generated between thecommon electrode CE and the shield electrode SHE. Accordingly, thepossibility of misalignment of liquid crystal molecules provided in theregion adjacent to the data lines DLm and DLm+1 may be lowered, thusreducing light leakage. Furthermore, an area of the light blockingmember BM, which will be described later and which is formed to preventlight leakage, may further be reduced or the light blocking member BMmay be omitted. Thus, an aperture ratio of the display device 1 mayfurther be increased.

Furthermore, an electric field generated between the data lines DLm andDLm+1 and the pixel electrode PE may be weakened by the shield electrodeSHE, thus providing an advantage of inhibiting crosstalk defects.

The light blocking member BM may be provided on a part of the firstsubpixel electrode PE1, a part of the second subpixel electrode PE2, apart of the second passivation layer PA2 and a part of the shieldelectrode SHE. The light blocking member BM may be provided on the firstlight blocking region BA1 of the first pixel region PA1 of the firstinsulation substrate SUB1. In some embodiments, the light blockingmember BM may directly contact a part of the first subpixel electrodePE1, a part of the second subpixel electrode PE2, a part of the secondpassivation layer PA2 and a part of the shield electrode SHE. The lightblocking member BM may at least partially overlap the gate line GLn andthe first, the second and the third thin film transistors Tr1, Tr2 andTr3. Furthermore, at least a part of the light blocking member BM mayfill the first contact hole CT1, the second contact hole CT2 and thesustain electrode contact hole CT3. The light blocking member BM mayinclude a light blocking pigment, for example black carbon, and aphotosensitive organic material.

In the display device 1 according to the present embodiment, the lightblocking member BM may be provided on the array substrate 100 togetherwith (i.e. over) the first, the second and the third thin filmtransistors Tr1, Tr2 and Tr3. Thus, light leakage caused by amisalignment between any of these elements, or a decrease in an apertureratio, may be prevented while improving transmittance.

A spacer member CS may be provided on the light blocking member BM, andmay directly contact the light blocking member BM. The spacer member CSmay directly contact the counterpart substrate 200, so as to maintain agap between the array substrate 100 and the counterpart substrate 200.In some embodiments, the spacer member CS may include a light blockingpigment, and may be made of the same material as that of the lightblocking member BM. In some embodiments, the spacer member CS may beformed integrally with the light blocking member BM, and the spacermember CS and the light blocking member BM may be formed simultaneouslythrough a single photolithography process using a slit mask, a halftonemask or the like.

In some embodiments, the spacer member CS may be arranged to overlap athin film transistor. In an exemplary embodiment, the spacer member CSmay be positioned so as to overlap at least one of the first thin filmtransistor Tr1, the second thin film transistor Tr2 and the third thinfilm transistor Tr3. Although the spacer member CS is depicted asoverlapping the first thin film transistor Tr1 in the drawings, this ismerely an example. As the spacer member CS may be arranged to overlap athin film transistor, the size of the light blocking member BM isreduced as compared to conventional configurations in which this is notthe case, thus improving the aperture ratio of the display device 1.

The counterpart substrate 200 will now be described.

The counterpart substrate 200 may include a second insulation substrateSUB2 and the common electrode CE.

The second insulation substrate SUB2 may be a transparent insulationsubstrate like the first insulation substrate SUB1. Furthermore, thesecond insulation substrate SUB2 may include polymers or plastics withhigh heat resistance. In some embodiments, the second insulationsubstrate SUB2 may have flexibility.

The common electrode CE may be provided on one surface of the secondinsulation substrate SUB2 that is directed toward, or facing, the firstinsulation substrate SUB1. The common electrode CE may be made of atransparent conductive material such as ITO and IZO. In someembodiments, the common electrode CE may be formed over substantiallythe entire surface of the second insulation substrate SUB2. The commonelectrode CE may receive common voltage Vcom applied thereto so as togenerate an electric field together with the pixel electrode PE.

The liquid crystal layer 300 will be described hereinafter.

The liquid crystal layer 300 may include a plurality of liquid crystalmolecules having dielectric anisotropy. The liquid crystal molecules maybe vertically aligned liquid crystal molecules interposed between thearray substrate 100 and the counterpart substrate 200, and alignedvertically with respect to the two substrates 100 and 200. When anelectric field is applied between the array substrate 100 and thecounterpart substrate 200, the liquid crystal molecules may rotate in aspecific direction between the array substrate 100 and the counterpartsubstrate 200 so as to either pass or block light. The term “rotate” asused herein may not only mean that the liquid crystal molecules actuallyrotate, but may also mean that the alignment of the liquid crystalmolecules changes by the electric field in any manner. In someembodiments, the liquid crystal layer 300 may include a reactive mesogenwhich undergoes polymerization reaction by light such as ultravioletrays, or may include a pre-tilt providing polymer produced by apolymerization reaction of a reactive mesogen. The pre-tilt providingpolymer may provide pre-tilt to the liquid crystal molecules even in thestate where no electric field is generated between the array substrate100 and the counterpart substrate 200.

FIG. 5 is a plan view schematically illustrating three pixels of thedisplay device according to an exemplary embodiment of the presentinventive concept. FIG. 6 is a plan view schematically illustrating anexemplary arrangement of insulation layers, a light blocking member,data lines and shield electrodes in the display device shown in FIG. 5.FIG. 7 is a schematic cross sectional view taken along line M1-M1′ ofFIG. 5 and FIG. 6. FIG. 8 is an enlarged perspective view illustrating apart of the light blocking member shown in FIG. 7. FIG. 9 is a schematiccross sectional view taken along line M2-M2′ of FIG. 5 and FIG. 6.

FIG. 5 to FIG. 9 illustrate pixels provided in the first pixel regionPA1, the second pixel region PA2 neighboring the first pixel region PA1in the first direction (or X direction), and a third pixel region PA3neighboring the second pixel region PA2 in the first direction (or Xdirection), that is, a 1×3 array of pixels. Furthermore, FIG. 5 to FIG.9 illustrate mainly the first light blocking region BA1 provided in thefirst pixel region PA1, a second light blocking region BA2 provided inthe second pixel region PA2, a third light blocking region BA3 providedin the third pixel region PA3, and the first, the second and the thirdthin film transistors Tr1, Tr2 and Tr3 provided in each of therespective light blocking regions BA1, BA2 and BA3. FIG. 5 and FIG. 6illustrate the first, the second and the third light blocking regionsBA1, BA2 and BA3 corresponding to the respective 1×3 array of pixels.

For the sake of convenience in description, FIG. 7 and FIG. 9 omit someof the components provided between the first insulation substrate SUB1and insulation layers of the array substrate 100, and also omit adetailed configuration of the counterpart substrate 200.

Referring to FIG. 5 to FIG. 9, the first pixel region PA1, the secondpixel region PA2 and the third pixel region PA3 may be arranged inparallel along the first direction (X direction). The boundary region EAmay be provided between the first pixel region PA1 and the second pixelregion PA2, and between the second pixel region PA2 and the third pixelregion PA3. The first data line DLm and the second data line DLm+1 maybe provided at both longitudinal sides of the first pixel region PA1,the second data line DLm+1 and a third data line DLm+2 may be providedat both longitudinal sides of the second pixel region PA2, and the thirddata line DLm+2 and a fourth data line DLm+3 may be provided at bothlongitudinal sides of the third pixel region PA3. In this case, thefirst data line DLm, the second data line DLm+1, the third data lineDLm+2 and the fourth data line DLm+3 may be provided in the respectiveboundary regions EAs. The shield electrode SHE may be provided aboveeach of the data lines DLm, DLm+1, DLm+2 and DLm+3 with the secondpassivation layer PA2 interposed therebetween.

As described above, the pixel regions PA1, PA2 and PA3 may includerespective light blocking regions BA1, BA2 and BA3. Specifically, thefirst pixel region PA1 may include the first light blocking region BA1,the second pixel region PA2 may include the second light blocking regionBA2, and the third pixel region PA3 may include the third light blockingregion BA3.

The first insulation layer ILA1 described above with reference to FIG. 2to FIG. 4 may be disposed in the first pixel region PA1, the secondinsulation layer ILA2 may be disposed in the second pixel region PA2,and a third insulation layer ILA3 may be disposed in the third pixelregion PA3. In an exemplary embodiment, the first insulation layer ILA1may be a first color filter including a first color pigment, the secondinsulation layer ILA2 may be a second color filter including a secondcolor pigment different from the first color pigment, and the thirdinsulation layer ILA3 may be a third color filter including a thirdcolor pigment different from both the first color pigment and the secondcolor pigment. In some embodiments, the first insulation layer ILA1 maybe a blue color filter, the second insulation layer ILA2 may be either agreen color filter or a red color filter, and the third insulation layerILA3 may be the other of the green color filter and the red colorfilter. In this case, as shown in FIG. 6 and FIG. 8, the firstinsulation layer ILA1 may have a thickness greater than the thickness ofthe second insulation layer ILA2 and the thickness of the thirdinsulation layer ILA3.

The insulation layers ILA1, ILA2, ILA3 neighboring each other may bespaced apart from each other in a portion of the boundary regionprovided between the light blocking regions. Alternatively, theinsulation layers ILA1, ILA2, ILA3 may partially overlap each other in aportion of the boundary region provided between the pixel regions andoutside the light blocking regions.

For example, as shown in FIG. 6 and FIG. 7, the first insulation layerILA1 and the second insulation layer ILA2 may be spaced apart from eachother in the boundary region EA between the first light blocking regionBA1 and the second light blocking region BA2. Similarly, the secondinsulation layer ILA2 and the third insulation layer ILA3 may be spacedapart from each other in the boundary region EA between the second lightblocking region BA2 and the third light blocking region BA3.Alternatively, the first insulation layer ILA1 and the second insulationlayer ILA2 may overlap each other in the boundary region EA between thefirst pixel region PA1 and the second pixel region PA2 and outside thelight blocking regions BA1 and BA2. Similarly, the second insulationlayer ILA2 and the third insulation layer ILA3 may overlap each other inthe boundary region EA between the second pixel region PA2 and the thirdpixel region PA3 and outside the light blocking regions BA2 and BA3.

The light blocking member BM may overlap or form the first lightblocking region BA1, the second light blocking region BA2 and the thirdlight blocking region BA3, and may extend in the first direction (or Xdirection). In other words, a part of the light blocking member BMoverlapping or forming the first light blocking region BA1, a part ofthe light blocking member BM overlapping or forming the second lightblocking region BA2, and a part of the light blocking member BMoverlapping or forming the third light blocking region BA3 may beconnected with each other.

As shown in FIG. 6, the light blocking member BM may be disposed on apart of the first insulation layer ILA1 to form the first light blockingregion BA1, a part of the second insulation layer ILA2 to form thesecond light blocking region BA2, and a part of the third insulationlayer ILA3 to form the third light blocking region BA3. Furthermore, asshown in FIG. 7, the light blocking member BM may fill the space betweenthe first insulation layer ILA1 and the second insulation layer ILA2 andthe space between the second insulation layer ILA2 and the thirdinsulation layer ILA3. Hereinafter, for the sake of convenience inexplanation, the part of the light blocking member BM forming the firstlight blocking region BA1 will be defined as a first part BM1, the partof the light blocking member BM forming the second light blocking regionBA2 will be defined as a second part BM2, and a part of the lightblocking member BM forming the boundary region EA between the firstlight blocking region BA1 and the second light blocking region BA2 ofthe first insulation substrate SUB1 will be defined as a third part BM3.In some embodiments, the first part BM1 may be disposed on the firstinsulation layer ILA1, the second part BM2 may be disposed on the secondinsulation layer ILA2, and the third part BM3 may be disposed in thespace between the first insulation layer ILA1 and the second insulationlayer ILA2. The first part BM1 may be disposed at one side of the thirdpart BM3 and the second part BM2 may be disposed at the other side ofthe third part BM3 in the first direction (or X direction).

The third part BM3 may have both sides open. More specifically, as shownin FIG. 8, both sides of the third part BM3 may open in the seconddirection (or Y direction), so that third part BM3 creates an openchannel allowing fluid flow along the direction of the arrows as shown.

When the minimum height from one surface SUB1 a of the first insulationsubstrate SUB1 to an upper surface of the first part BM1 is referred toas a first height H1, the minimum height from one surface SUB1 a of thefirst insulation substrate SUB1 to an upper surface of the second partBM2 is referred to as a second height H2, and the minimum height fromone surface SUB1 a of the first insulation substrate SUB1 to an uppersurface of the third part BM3 is referred to as a third height H3, thethird height H3 may be lower than each of the first height H1 and thesecond height H2. No separate insulation layer may be provided in theboundary region EA between the first insulation layer ILA1 and thesecond insulation layer ILA2. The light blocking member BM may havenatural stepped portions. Therefore, the third height H3 may be lowerthan each of the first height H1 and the second height H2, so that achannel or depression is formed between first part BM1 and second partBM2.

In some embodiments, when the first insulation layer ILA1 is a bluecolor filter, the second insulation layer ILA2 is either a green colorfilter or a red color filer, and the third insulation layer ILA3 is theother of the green color filter and the red color filer, the firstinsulation layer ILA1 may be thicker than the second insulation layerILA2 and the third insulation layer ILA3. In this case, the first heightH1 may be higher than the second height H2. That is, a differencebetween the first height H1 and the second height H2 may be caused by athickness difference between the first insulation layer ILA1 and thesecond insulation layer ILA2.

The spacer member CS may be provided on the light blocking member BM. Insome embodiments, when the thickness of the first insulation layer ILA1is thicker than the thickness of the second insulation layer ILA2 andthe thickness of the third insulation layer ILA3, the spacer member CSmay be disposed to overlap the first insulation layer ILA1. That is, thespacer member CS may be disposed on the first part BM1, and in thiscase, the second part BM2 may act as an auxiliary spacer member.Furthermore, the spacer member CS may be disposed on the firstinsulation layer ILA1, which is relatively thick, thereby reducing thethickness of the spacer member CS itself. The degree of compression ofthe spacer member CS may be in proportion to the thickness of the spacermember CS itself. Thus, when the spacer member CS is disposed on thefirst insulation layer ILA1 which is relatively thick, the thickness ofthe spacer member CS itself may be reduced, thereby relatively reducinga deformation of the spacer member CS when a force is applied from anexternal source.

Disposing the spacer member CS on the first part BM1 may thus providethe advantage of reducing a height difference between the spacer memberCS and an auxiliary spacer member, for example, the second part BM2, byusing a thickness difference between the first insulation layer ILA1 andthe second insulation layer ILA2.

The spacer member CS may include a light blocking pigment, and may bemade of the same material as that of the light blocking member BM.Furthermore, in some embodiments, the spacer member CS may be formedintegrally with the light blocking member BM. In this case, the spacermember CS and the light blocking member BM may be formed through aphotolithography process using a single mask.

For example, when the light blocking member BM is made of a negativetype photosensitive material, the light blocking member BM and thespacer member CS may be formed simultaneously using a halftone maskincluding a light transmitting pattern, a light blocking pattern and asemitransmitting pattern. In this case, the light transmitting patternmay correspond to the spacer member CS, the light blocking pattern maycorrespond to the regions outside the light blocking regions BA1, BA2and BA3, and the semitransmitting pattern may correspond to the lightblocking regions BA1, BA2 and BA3 excluding the spacer member CS. Inthis case, the height difference between the third part BM3 and thefirst part BM1, and the height difference between the third part BM3 andthe second part BM2, may be caused by the space between the firstinsulation layer ILA1 and the second insulation layer ILA2.

Alternatively, in another exemplary embodiment, when the light blockingmember BM is made of a negative type photosensitive material, the lightblocking member BM and the spacer member CS may be formed simultaneouslyusing a halftone mask including a light transmitting pattern, a lightblocking pattern, a first semitransmitting pattern and a secondsemitransmitting pattern of which transmittance is lower than that ofthe first semitransmitting pattern. In this case, the light transmittingpattern may correspond to the spacer member CS, and the light blockingpattern may correspond to the region outside the light blocking regionsBA1, BA2 and BA3. In addition, the first semitransmitting pattern andthe second semitransmitting pattern may correspond to the light blockingregions BA1, BA2 and BA3. Specifically, the second semitransmittingpattern may correspond to the boundary regions EAs between the lightblocking regions BA1, BA2 and BA3, and the first semitransmittingpattern may correspond to the portions of the light blocking regionsBA1, BA2 and BA3 besides those corresponding to the secondsemitransmitting pattern. In this case, the height difference betweenthe third part BM3 and the first part BM1, and the height differencebetween the third part BM3 and the second part BM2, may be caused partlyby the space between the first insulation layer ILA1 and the secondinsulation layer ILA2, and partly by a transmittance difference betweenthe first semitransmitting pattern and the second semitransmittingpattern. That is, the third part BM3 may be hardened by the quantity oflight which is relatively smaller than that of the first part BM1 andthe second part BM2, thus partly causing the height difference betweenthe third part BM3 and the first part BM1 and the height differencebetween the third part BM3 and the second part BM2.

When a force is applied from an external source to the display device 1,the spacer member CS interposed between the array substrate 100 and thecounterpart substrate 200 may absorb a part of the external force, so asto be compressed. In this case, a gap between the array substrate 100and the counterpart substrate 200 may be maintained at a predeterminedlevel by the first part BM1 and the second part BM2, thereby securing aspace for enabling the liquid crystal layer 300 to be fully spread.

Meanwhile, when a larger force is applied from an external source to thedisplay device 1, the spacer member CS may be completely compressed, andthe counterpart substrate 200 may directly contact the first part BM1and/or the second part BM2. In addition, the first part BM1 and/or thesecond part BM2 may be partially compressed. In this case, thedepression formed by the third part BM3 may allow liquid crystal layer300 to more freely flow away from the compressed area. Furthermore, bothsides of the third part BM3 in the second direction (or Y direction) maybe open, thereby securing a path for flow of the liquid crystal layer300 in the second direction (or Y direction). Thus, degradation ofdisplay quality which may be caused when the liquid crystal layer 300 isnot fully spread may be prevented. Thus, a display device 1 withimproved reliability according to the present inventive concept may beprovided.

FIG. 10 is a plan view of a modified embodiment of the display deviceshown in FIG. 5, schematically illustrating another exemplaryarrangement of insulation layers, a light blocking member, data linesand shield electrodes in the display device. FIG. 11 is a schematiccross sectional view taken along line M1-M1′ of FIG. 5 and FIG. 10. FIG.12 is a schematic cross sectional view taken along line M2-M2′ of FIG. 5and FIG. 10.

In a display device 2 according to the present embodiment, an arraysubstrate 100 a may have a structure partially different from thestructure of the array substrate 100 described above with reference toFIG. 5 to FIG. 9. Specifically, the array substrate 100 a may bedifferent from the array substrate 100 described above with reference toFIG. 5 to FIG. 9, in that the former includes insulation layersoverlapping each other in the boundary regions EAs. However, othercomponents are substantially the same or similar. Therefore, redundantexplanation will be omitted and description will focus primarily on thedifferences between the embodiments.

Referring to FIG. 10 to FIG. 12, the first insulation layer ILA1 and thesecond insulation layer ILA2 may partially overlap each other in theboundary region EA between the first light blocking region BA1 and thesecond light blocking region BA2, as illustrated in FIG. 10 and FIG. 11.Similarly, the second insulation layer ILA2 and the third insulationlayer ILA3 may partially overlap in the boundary region EA between thesecond light blocking region BA2 and the third light blocking regionBA3. Furthermore, as shown in FIG. 12, the first insulation layer ILA1and the second insulation layer ILA2 may partially overlap in theboundary region EA between the first pixel region PA1 and the secondpixel region PA2, and outside the light blocking regions BA1 and BA2.Similarly, the second insulation layer ILA2 and the third insulationlayer ILA3 may partially overlap in the boundary region EA between thesecond pixel region PA2 and the third pixel region PA3 and outside thelight blocking regions BA2 and BA3.

As shown in FIG. 10 and FIG. 11, the light blocking member BMa may beprovided on a part of the first insulation layer ILA1 to form the firstlight blocking region BA1, a part of the second insulation layer ILA2 toform the second light blocking region BA2, and a part of the thirdinsulation layer ILA3 to form the third light blocking region BA3.Furthermore, the light blocking member BM may be provided on the overlapbetween the first insulation layer ILA1 and the second insulation layerILA2, and on the overlap between the second insulation layer ILA2 andthe third insulation layer ILA3. Hereinafter, for the sake ofconvenience in description, the part of the light blocking member BMaoverlapping or forming the first light blocking region BA1 will bedefined as a first part BMa1, the part of the light blocking member BMaoverlapping or forming the second light blocking region BA2 will bedefined as a second part BMa2, and a part of the light blocking memberBMa overlapping the boundary region EA between the first light blockingregion BA1 and the second light blocking region BA2 will be defined as athird part BMa3. In some embodiments, the first part BMa1 may bedisposed on the first insulation layer ILA1, the second part BMa2 may bedisposed on the second insulation layer ILA2, and the third part BMa3may be disposed on the overlap between the first insulation layer ILA1and the second insulation layer ILA2.

The third part BMa3 may have both sides open in the second direction (orY direction), like the third part BM3 described above with reference toFIG. 8.

When the minimum height from one surface SUB1 a of the first insulationsubstrate SUB1 to an upper surface of the first part BMa1 is referred toas a first height H1 a, the minimum height from one surface SUB1 a ofthe first insulation substrate SUB1 to an upper surface of the secondpart BMa2 is referred to as a second height H2 a, and the minimum heightfrom one surface SUB1 a of the first insulation substrate SUB1 to anupper surface of the third part BMa3 is referred to as a third height H3a, the third height H3 a may be lower than each of the first height H1 aand the second height H2 a. That is, a stepped portion may exist betweenthe first part BMa1 and the third part BMa3, and likewise a steppedportion may exist between the second part BMa2 and the third part BMa3,so that a channel or depression is formed between first part BMa1 andsecond part BMa2.

A spacer member CSa may be provided on the light blocking member BMa. Insome embodiments, when the first insulation layer ILA1 is formed to havea thickness greater than the thickness of the second insulation layerILA2 and the thickness of the third insulation layer ILA3, the spacermember CSa may be disposed to overlap the first insulation layer ILA1.That is, the spacer member CSa may be provided on the first part BMa1.

The spacer member CSa may include a light blocking pigment, and may bemade of the same material as that of the light blocking member BMa.Furthermore, in some embodiments, the spacer member CSa may be formedintegrally with the light blocking member BMa. In this case, the spacermember CSa and the light blocking member BMa may be formed through aphotolithography process using a single mask.

For example, when the light blocking member BMa is made of a negativetype photosensitive material, the light blocking member BMa and thespacer member CSa may be formed simultaneously using a halftone maskincluding a light transmitting pattern, a light blocking pattern, afirst semitransmitting pattern and a second semitransmitting patternwhose transmittance is lower than that of the first semitransmittingpattern. In this case, the light transmitting pattern may correspond tothe spacer member CSa, and the light blocking pattern may correspond tothe region outside the light blocking regions BA1, BA2 and BA3. Inaddition, the first semitransmitting pattern and the secondsemitransmitting pattern may correspond to the light blocking regionsBA1, BA2 and BA3. Specifically, the second semitransmitting pattern maycorrespond to the boundary regions EAs of the light blocking regionsBA1, BA2 and BA3, and the first semitransmitting pattern may correspondto the portions of the light blocking regions BA1, BA2 and BA3 outsidethe portion corresponding to the second semitransmitting pattern. Inthis case, the height difference between the third part BMa3 and thefirst part BMa1, and the height difference between the third part BMa3and the second part BMa2, may be caused by a transmittance differencebetween the first semitransmitting pattern and the secondsemitransmitting pattern. That is, the third part BMa3 may be hardenedby a quantity of light which is relatively smaller than that incident tothe first part BMa1 and the second part BMa2, thus causing the heightdifference between the third part BMa3 and the first part BMa1, and theheight difference between the third part BMa3 and the second part BMa2.

Since other components are substantially the same or similar as thosedescribed with reference to FIG. 5 to FIG. 9, detailed descriptionthereof will be omitted.

FIG. 13 is a schematic cross sectional view of the display deviceaccording to another embodiment of the present inventive concept, takenalong line L3-L3′ of FIG. 2. FIG. 14 is a schematic cross sectional viewof the display device according to another embodiment of the presentinventive concept, taken along line L4-L4′ of FIG. 2.

Referring to FIG. 13 and FIG. 14, a display device 3 according to thepresent embodiment may include an array substrate 100 b, a counterpartsubstrate 200 a facing the array substrate 100 b, and a liquid crystallayer 300 interposed between the array substrate 100 b and thecounterpart substrate 200 a. The display device 3 may further include apair of polarizers (not shown) attached to outer surfaces of the arraysubstrate 100 b and the counterpart substrate 200 a.

Unlike the display device 1 described above with reference to FIG. 2 toFIG. 4, the display device 3 according to the present embodiment mayinclude a light blocking member BMb and a spacer member CSb provided onthe counterpart substrate 200 a.

The array substrate 100 b differs from the array substrate 100 describedabove with reference to FIG. 2 to FIG. 4, in that the former does notinclude the light blocking member BMb and the spacer member CSb. Othercomponents may be substantially the same. Therefore, detaileddescription of each such other component will be omitted.

The counterpart substrate 200 a may include the second insulationsubstrate SUB2, the light blocking member BMb and the common electrodeCE.

The second insulation substrate SUB2 may be a transparent insulationsubstrate like the first insulation substrate SUB1.

The common electrode CE may be provided on one surface of the secondinsulation substrate SUB2 that faces the first insulation substrateSUB1. The common electrode CE may be made of a transparent conductivematerial such as ITO and IZO.

The light blocking member BMb may be provided on the common electrodeCE.

The light blocking member BMb may overlap the first light blockingregion BA1 of the first pixel region PA1 of the first insulationsubstrate SUB1. The light blocking member BMb may cover the gate lineGLn and the first, the second and the third thin film transistors Tr1,Tr2 and Tr3. Furthermore, the light blocking member BMb may cover thefirst contact hole CT1, the second contact hole CT2 and the sustainelectrode contact hole CT3. The light blocking member BMb may include alight blocking pigment, for example, black carbon, and/or aphotosensitive organic material.

The spacer member CSb may be provided on the light blocking member BMb,and may directly contact the light blocking member BMb. The spacermember CSb may directly contact the array substrate 100 b, and maymaintain a gap between the array substrate 100 b and the counterpartsubstrate 200 a. In some embodiments, the spacer member CSb may includea light blocking pigment, and may be made of the same material as thatof the light blocking member BMb. In some embodiments, the spacer memberCSb may be formed integrally with the light blocking member BMb, and thespacer member CSb and the light blocking member BMb may be formedsimultaneously through a single photolithography process using a slitmask, a halftone mask or the like.

In some embodiments, the spacer member CSb may be arranged to overlap athin film transistor. In an exemplary embodiment, the spacer member CSbmay be arranged to overlap at least one of the first thin filmtransistor Tr1, the second thin film transistor Tr2 and the third thinfilm transistor Tr3. Although the spacer member CSb is depicted asoverlapping the first thin film transistor Tr1 in the drawings, this ismerely an example, and it may alternatively overlap any other transistoror other structure.

Other components may be the same as those described above with referenceto FIG. 2 to FIG. 4, and therefore any detailed description thereof willbe omitted.

FIG. 15 is a plan view schematically illustrating an exemplaryarrangement of insulation layers, a light blocking member, data linesand shield electrodes in the display device according to anotherembodiment of the present inventive concept. FIG. 16 is a schematiccross sectional view taken along line M1-M1′ of FIG. 5 and FIG. 15. FIG.17 is an enlarged perspective view illustrating a part of the lightblocking member shown in FIG. 16. FIG. 18 is a schematic cross sectionalview taken along line M2-M2′ of FIG. 5 and FIG. 16.

Referring to FIG. 15 to FIG. 18, the array substrate 100 b of thedisplay device 3 differs from the array substrate 100 described abovewith reference to FIG. 5 to FIG. 9, in that the former does not includethe light blocking member BMb. Various other components may besubstantially the same.

For example, the first pixel region PA1, the second pixel region PA2 andthe third pixel region PA3 may be arranged in parallel along the firstdirection (X direction), and the boundary region EA may be providedbetween the first pixel region PA1 and the second pixel region PA2 andbetween the second pixel region PA2 and the third pixel region PA3. Thefirst data line DLm and the second data line DLm+1 may be provided atboth longitudinal sides of the first pixel region PA1, the second dataline DLm+1 and the third data line DLm+2 may be provided at bothlongitudinal sides of the second pixel region PA2, and the third dataline DLm+2 and the fourth data line DLm+3 may be provided at bothlongitudinal sides of the third pixel region PA3. In this case, thefirst data line DLm, the second data line DLm+1, the third data lineDLm+2 and the fourth data line DLm+3 may be provided in the respectiveboundary regions EAs. The shield electrode SHE may be provided aboveeach of the data lines DLm, DLm+1, DLm+2 and DLm+3 with the secondpassivation layer PA2 interposed therebetween.

The first pixel region PA1 may include the first light blocking regionBA1, the second pixel region PA2 may include the second light blockingregion BA2, and the third pixel region PA3 may include the third lightblocking region BA3.

The first insulation layer ILA1 may be disposed in the first pixelregion PA1, the second insulation layer ILA2 may be disposed in thesecond pixel region PA2, and the third insulation layer ILA3 may bedisposed in the third pixel region PA3.

The first insulation layer ILA1 and the second insulation layer ILA2 maybe spaced apart from each other in the boundary region EA between thefirst light blocking region BA1 and the second light blocking regionBA2. Similarly, the second insulation layer ILA2 and the thirdinsulation layer ILA3 may be spaced apart from each other in theboundary region EA between the second light blocking region BA2 and thethird light blocking region BA3. Alternatively, as shown in FIG. 18, thefirst insulation layer ILA1 and the second insulation layer ILA2 maypartially overlap each other in the boundary region EA between the firstpixel region PA1 and the second pixel region PA2. Similarly, the secondinsulation layer ILA2 and the third insulation layer ILA3 may partiallyoverlap each other in the boundary region EA between the second pixelregion PA2 and the third pixel region PA3.

The light blocking member BMb may be provided on one surface of thesecond insulation substrate SUB2 facing the array substrate 100 b.Although not shown in the drawings, a common electrode may be interposedbetween the light blocking member BMb and the second insulationsubstrate SUB2 as described above with reference to FIG. 13 and FIG. 14.The light blocking member BMb may overlap or form the first lightblocking region BA1, the second light blocking region BA2 and the thirdlight blocking region BA3, and may extend in the first direction (or Xdirection). In other words, a part of the light blocking member BMboverlaps or forms the first light blocking region BA1, a part of thelight blocking member BMb overlaps or forms the second light blockingregion BA2, and a part of the light blocking member BMb overlaps orforms the third light blocking region BA3, and each of these parts maybe connected with each other.

The part of the light blocking member BMb overlapping the first lightblocking region BA1 will be defined as a first part BMb1, the part ofthe light blocking member BMb overlapping the second light blockingregion BA2 will be defined as a second part BMb2, and a part of thelight blocking member BMb overlapping the boundary region EA between thefirst light blocking region BA1 and the second light blocking region BA2will be defined as a third part BMb3.

The third part BMb3 may have both sides open. More specifically, asshown in FIG. 16, both sides of the third part BMb3 may open in thesecond direction (or Y direction), so that a channel or depression isformed between first part BMb1 and second part BMb2.

When the minimum height from one surface SUB2 a of the second insulationsubstrate SUB2 to an upper surface of the first part BMb1 is referred toas a first height H1 b, the minimum height from one surface SUB2 a ofthe second insulation substrate SUB2 to an upper surface of the secondpart BMb2 is referred to as a second height H2 b, and the minimum heightfrom one surface SUB2 a of the second insulation substrate SUB2 to anupper surface of the third part BMb3 is referred to as a third height H3b, the third height H3 b may be lower than each of the first height H1 band the second height H2 b. In some embodiments, the first height H1 band the second height H2 b may be the same. In another embodiment, thefirst height H1 b and the second height H2 b may be different from eachother. In some embodiments, when the first insulation layer ILA1 isformed to have a thickness greater than the thickness of the secondinsulation layer ILA2 and the thickness of the third insulation layerILA3, the first height H1 b may be greater than the second height H2 b.

The spacer member CSb may be provided on the light blocking member BMb.In some embodiments, when the thickness of the first insulation layerILA1 is greater than the thickness of the second insulation layer ILA2and the thickness of the third insulation layer ILA3, the spacer memberCSb may be disposed to overlap the first insulation layer ILA1. That is,the spacer member CSb may be disposed on the first part BMb1, and inthis case, the second part BMb2 may act as an auxiliary spacer member.Furthermore, the spacer member CSb may be disposed on the first partBMb1, which is relatively thick, and may overlap the first insulationlayer ILA1, thereby reducing the thickness of the spacer member CSbitself.

The spacer member CSb may include a light blocking pigment, and may bemade of the same material as that of the light blocking member BMb.Furthermore, in some embodiments, the spacer member CSb may be formedintegrally with the light blocking member BMb. In this case, the spacermember CSb and the light blocking member BMb may be formed through aphotolithography process using a single mask.

In an exemplary embodiment, when the light blocking member BMb is madeof a negative type photosensitive material, the light blocking memberBMb and the spacer member CSb may be formed simultaneously using ahalftone mask including a light transmitting pattern, a light blockingpattern, a first semitransmitting pattern and a second semitransmittingpattern whose transmittance is lower than that of the firstsemitransmitting pattern. In this case, the light transmitting patternmay correspond to the spacer member CSb, and the light blocking patternmay correspond to the region outside the light blocking regions BA1, BA2and BA3. In addition, the second semitransmitting pattern may correspondto the third part BMb3, and the first semitransmitting pattern maycorrespond to a portion of the first part BMb1 which does not overlapthe spacer member CSb as well as to the second part BMb2. The third partBMb3 may be hardened by a quantity of light less than that incident tothe first part BMb1 and the second part BMb2, thus causing a heightdifference between the third part BMb3 and the first part BMb1 and aheight difference between the third part BMb3 and the second part BMb2.

Since other components are substantially the same or similar as thosedescribed with reference to FIG. 5 to FIG. 9, detailed descriptionthereof will be omitted.

FIG. 19 is a plan view of a modified embodiment of the display deviceshown in FIG. 15, schematically illustrating another exemplaryarrangement of insulation layers, a light blocking member, data linesand shield electrodes in the display device. FIG. 20 is a schematiccross sectional view taken along line M1-M1′ of FIG. 19. FIG. 21 is aschematic cross sectional view taken along line M2-M2′ of FIG. 5 andFIG. 19.

Referring to FIG. 19 to FIG. 21, an array substrate 100 c of a displaydevice 4 of the present embodiment differs from the array substrate 100a described above with reference to FIG. 10 to FIG. 12, in that thelight blocking member BMb is not disposed in the array substrate 100 c.Various other components may be substantially the same.

The first insulation layer ILA1 and the second insulation layer ILA2 maypartially overlap each other in the boundary region EA between the firstlight blocking region BA1 and the second light blocking region BA2.Similarly, the second insulation layer ILA2 and the third insulationlayer ILA3 may partially overlap each other in the boundary region EAbetween the second light blocking region BA2 and the third lightblocking region BA3. Furthermore, as shown in FIG. 20, the firstinsulation layer ILA1 and the second insulation layer ILA2 may partiallyoverlap each other in the boundary region EA outside the first lightblocking region BA1 and the second light blocking region BA2. Similarly,the second insulation layer ILA2 and the third insulation layer ILA3 maypartially overlap each other in the boundary region EA outside thesecond light blocking region BA2 and the third light blocking regionBA3.

The light blocking member BMb may be the same as those described abovewith reference to FIG. 15 to FIG. 18. Specifically, the light blockingmember BMb may include a first part BMb1 overlapping or forming thefirst light blocking region BA1, a second part BMb2 overlapping orforming the second light blocking region BA2, and a third part BMb3overlapping the boundary region EA between the first light blockingregion BA1 and the second light blocking region BA2. In the presentembodiment, the first part BMb1 of the light blocking member BMb mayoverlap the first insulation layer ILA1, the second part BMb2 of thelight blocking member BMb may overlap the second insulation layer ILA2,and the third part BMb3 of the light blocking member BMb may overlap thearea containing boh the first insulation layer ILA1 and the secondinsulation layer ILA2.

Since other components are substantially the same or similar with thosedescribed with reference to FIG. 10 to FIG. 12 and FIG. 15 to FIG. 18,detailed description thereof will be omitted.

While the present inventive concept has been particularly shown anddescribed with reference to exemplary embodiments thereof, these aremerely examples and the present disclosure is not limited thereto. Itwill be understood by those of ordinary skill in the art that variouschanges in form and details may be made therein without departing fromthe spirit and scope of the present inventive concept as defined by thefollowing claims. For example, each component described in theembodiments of the present disclosure can be modified. Furthermore,differences related to the modifications and applications should beunderstood as being included in the scope of the present inventiveconcept defined in the appended claims. Various features of the abovedescribed and other embodiments can be mixed and matched in any manner,to produce further embodiments consistent with the invention.

What is claimed is:
 1. A display device comprising: an array substrate;a counterpart substrate facing the array substrate; and a liquid crystallayer interposed between the array substrate and the counterpartsubstrate; wherein the array substrate includes: a first insulationsubstrate including a first pixel region having a first light blockingregion, and a second pixel region disposed adjacent to the first pixelregion in a first direction and having a second light blocking region; afirst insulation layer disposed on the first light blocking region ofthe first insulation substrate; a second insulation layer disposed onthe second light blocking region of the first insulation substrate; alight blocking member including a first part disposed on the first lightblocking region of the first insulation substrate and on the firstinsulation layer, a second part disposed on the second light blockingregion of the first insulation substrate and on the second insulationlayer, and a third part disposed on a boundary between the first lightblocking region of the first insulation substrate and the second lightblocking region of the first insulation substrate, the third part beingconnected to the first part and the second part; and a spacer memberdisposed on the light blocking member and contacting the counterpartsubstrate, and wherein a minimum height from an upper surface of thefirst insulation substrate to an upper surface of the third part islower than a minimum height from the upper surface of the firstinsulation substrate to an upper surface of the first part and lowerthan a minimum height from the upper surface of the first insulationsubstrate to an upper surface of the second part.
 2. The display deviceof claim 1, wherein the first insulation layer and the second insulationlayer are spaced apart from each other at the boundary between the firstlight blocking region and the second light blocking region, and thethird part is disposed in a space between the first insulation layer andthe second insulation layer.
 3. The display device of claim 1, whereinthe first insulation layer and the second insulation layer overlap eachother at the boundary between the first light blocking region and thesecond light blocking region, and the third part is disposed on anoverlap between the first insulation layer and the second insulationlayer.
 4. The display device of claim 1, wherein the spacer memberincludes a light blocking pigment.
 5. The display device of claim 4,wherein the spacer member is formed integrally with the light blockingmember.
 6. The display device of claim 1, wherein the first part isdisposed at one side of the third part, and the second part is disposedat an opposing side of the third part.
 7. The display device of claim 1,wherein the third part forms a channel extending in a second directionintersecting the first direction.
 8. The display device of claim 1,wherein the first insulation layer includes a first color pigment, andthe second insulation layer includes a second color pigment differentfrom the first color pigment.
 9. The display device of claim 1, whereinthe first color pigment is a blue pigment, and the spacer member isdisposed on the first part.
 10. The display device of claim 1, whereinthe array substrate further includes a thin film transistor disposed inthe first light blocking region of the first insulation substrate, andthe spacer member overlaps the thin film transistor.
 11. A displaydevice comprising: an array substrate; a counterpart substrate facingthe array substrate; and a liquid crystal layer interposed between thearray substrate and the counterpart substrate; wherein the arraysubstrate includes a first insulation substrate having a first pixelregion having a first light blocking region, and a second pixel regiondisposed adjacent to the first pixel region in a first direction andhaving a second light blocking region; the counterpart substrateincludes: a second insulation substrate; a light blocking memberdisposed on the second insulation substrate facing the array substrate,and overlapping the first light blocking region and the second lightblocking region; and a spacer member which is disposed on the lightblocking member and which contacts the array substrate; wherein thelight blocking member includes a first part, a second part differentfrom the first part, and a third part different from the first part andthe second part, wherein a minimum height from one surface of the secondinsulation substrate to an upper surface of the third part is lower thana minimum height from the one surface of the second insulation substrateto an upper surface of the first part and lower than a minimum heightfrom the one surface of the second insulation substrate to an uppersurface of the second part.
 12. The display device of claim 11, whereinthe minimum height from the one surface of the second insulationsubstrate to the upper surface of the first part is higher than theminimum height from one surface of the second insulation substrate tothe upper surface of the second part.
 13. The display device of claim12, wherein the spacer member is disposed on the first part.
 14. Thedisplay device of claim 11, wherein the first part is disposed at oneside of the third part, and the second part is disposed at an opposingside of the third part.
 15. The display device of claim 11, the thirdpart forms a channel extending in a second direction intersecting thefirst direction.
 16. The display device of claim 11, wherein the spacermember includes a light blocking pigment.
 17. The display device ofclaim 16, wherein the spacer member is formed integrally with the lightblocking member.
 18. The display device of claim 11, wherein the arraysubstrate further includes a first insulation layer disposed on thefirst light blocking region of the first insulation substrate andoverlapping the first part, and a second insulation layer disposed onthe second light blocking region of the first insulation substrate andoverlapping the second part, and the third part overlaps a boundarybetween the first light blocking region and the second light blockingregion.
 19. The display device of claim 18, wherein the first insulationlayer includes a first color pigment, and the second insulation layerincludes a second color pigment different from the first color pigment.20. The display device of claim 18, wherein the first color pigment is ablue pigment, and the spacer member is disposed on the first part.